ADP: An Adaptive Downgrade Predictor for Hybrid Multi-Die Architecture

Downgrade prediction technique speculatively writes dirty data back from cache to memory by predicting the last-touch or last-write-touch of a cache block, allowing subsequent memory access requests from other cores to directly read data from the LLC or memory, hiding the additional delay caused by coherence activities. Previous downgrade prediction techniques, namely LDP, which typically employ a PAp approach to maintain prediction coverage, suffers from low coverage when the program does not exhibit enough repeated patterns within a block address. A way to address this issue is to employ a PAg approach, which is called GDP in this paper, to allow sharing of a same signature across different other block addresses, with the disadvantage of higher misprediction ratio. This paper proposes an Adaptive Downgrade Predictor, ADP, which makes us of a Choice Predictor, to select the best predictor for a given block address at the runtime to achieve high coverage in GDP while maintaining low misprediction like LDP for each application. The experimental results show that the average prediction coverage of LDP and GDP are 79% and 72.5% respectively, with the average misprediction rate of are 1.8% and 10.2% respectively. With ADP, the average prediction coverage is 86.3%, increased by 7.3% as compared to LDP and by 13.8% as compared to GDP, with the average misprediction rate of 3.3%, significantly decreased by 6.9% as compared to GDP but slightly increased by 1.5% as compared to LDP.