A High-performance Hardware Implementation of SC Polar Decoder Based on Convolutional Neural Networks

Polar codes are capacity-achieving channel codes and have recently been adopted for the control channels in fifth-generation (5G) and the next generation of communication technology. However, existing successive cancellation (SC) polar decoders experience significant processing latency due to their sequential nature, which limits the practical applicability of polar codes. In this paper, we propose a hardware-efficient implementation of a SC polar decoder, assisted by convolutional neural network (CNN). The polar decoder is divided into multiple sub-blocks, with each sub-block replaced by a sub-CNN decoder that takes log-likelihood ratios (LLRs) and the frozen pattern as inputs. Additionally, we also design computational modules that can compute 16 LLRs in parallel at one clock cycle to reduce decoding latency. Through simulation results, under the PUCCH channel of 5G communication, the proposed decoder achieves a block error rate (BLER) performance with 0.7% improvement when comparing to the conventional SC polar decoder. We have synthesized our design in TSMC 28-nm CMOS process and it occupies an area of 0.1278 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and operates at a maximum clock frequency of 1315 MHz for polar code (1024,256). Our decoder delivers a throughput of 4.842 Gb/s and an area efficiency of 38.89 Gb/s/ mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, which is 119% better than the state-of-the-art implementation.