High-Speed and Secure ECC Processor for Chinese SM2 Using Modified Karatsuba Multiplier Based on FPGA

High-performance throughput is a critical issue in the hardware implementation of elliptic curve cryptography (ECC). This paper presents the construction of a high-speed ECC processor based on Mersenne-like prime fields. The subtractive form of the Radix-4 Karatsuba algorithm is introduced, along with a 2-level Karatsuba multiplier that eliminates the impact of bit-width expansion during iterations through pre-preprocessing. An improved Montgomery scalar multiplication algorithm is employed, allowing for the parallel execution of point addition and point doubling operations, effectively resisting SPA attacks. Computational steps are arranged rationally, and a scheduling scheme is proposed to maximize the efficiency of the computational units, thereby reducing the execution cycle of scalar multiplication operations. By adopting the afore-mentioned Karatsuba multiplier and improved Montgomery scalar multiplication scheduling scheme, the ECC processor for SM2 P256 field is implemented on the Virtex-7 FPGA platform, performing a scalar multiplication operation every 47us, utilizing 35.5k LUTs and 200 DSPs.