Analysis of Dual configurations of EDT for Compression Techniques in chip testing in VLSI

Design For Testability Plays an Important role in the silicon industry so it helps check the faults of the design in the post and pre-integrated chip manufacturing industry. Faults play a vital role in destroying the whole chip, if we are integrating the millions of transistors in a single chip causes many unwanted faults. To reduce the faults, we have so many techniques to reduce the test time and test data volume. Another type of technique we have followed here is dual configuration for EDT. It will be supported for both input configurations. Normally we concentrate on the Dual or Multi Configuration techniques for the design. According to the requirement of the industry level, mostly concentrate on the general configuration on the DFT level. The design will work for both the conditions EDT Configurations which have higher configurations and lower configurations. This design helps to check the possibility conditions of the different configurations; there is no need to change the entire design for the different design configurations for the same netlist. This design will help to reduce the burden of the DFT designer and the cost of the customer. The tool has the privilege of working with the dual set configuration for higher and lower, tool has certain limitations for the dual/Multiple EDT Configurations.