A 71.5-dB SNDR 475-MS/s Ringamp-Based Pipelined SAR ADC With On-Chip Bit-Weight Calibration

This article presents a single-channel 13-bit pipelined successive-approximation register (SAR) analog-to-digital converter (ADC). To achieve energy-efficient residue amplification, a ring amplifier (ringamp) with optimized biasing and common-mode feedback (CMFB) is utilized. The inter-stage gain and digital-to-analog converter (DAC) mismatch are calibrated by leveraging the proposed auxiliary-latch-based comparison-threshold dithering (CTD) and separate-averaging algorithm. This calibration achieves fast convergence, requiring only 4096 dither-injected samples for background gain-error correction. Fabricated in a 22-nm CMOS process, the ADC consumes 9.93 mW at 475 MS/s and achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 71.5 dB, yielding a Schreier figure of merit (FoMS) of 175.3 dB and a Walden figure of merit (FoMW) of 6.8 fJ/conversion-step.