A 0.014%/V LS and -73.5 dB PSRR 5-T voltage reference with enhanced self regulation

This paper proposes a 5-transistor (5-T) voltage reference (VR) with enhanced self regulation for low-voltage and low-power applications. In the proposed circuit, the gate feedback with the source degeneration is applied to a transistor to form the enhanced self regulation to reduce the impact of the supply voltage (VDD) on the reference voltage (VREF). Moreover, a stacked gate-source connected transistor further increases the impedance from the VDD to ground. In this way, both line sensitivity (LS) and power supply rejection ratio (PSRR) can be improved without any additional current overhead. The proposed VR is fabricated in a 0.18 μm CMOS process, while 10 samples have been measured. It can provide a VREF of 387.1 mV and consume a power consumption of 50.4 pW at 27°C. The results show that the average LS reaches 0.014%/V when the VDD varies from 0.6 V to 5 V. Additionally, the PSRR is -73.5 dB and -49.4 dB at 10 Hz and 100 Hz respectively. The average temperature coefficient (TC) is 80.8 ppm/°C without any trimming from 0°C to 100°C. The total area of the proposed VR is only 0.0038 mm2.