Analyzing the Impact of Gate Oxide Screening on Interface Trap Density in SiC Power MOSFETs Using a Novel Temperature-Triggered Method

This work introduces a novel temperature-triggered threshold voltage shift (T3VS) method to study the energy-dependent Dit distribution close to the conduction band edge in commercial 1.2 kV 4H-SiC MOSFETs with planar and trench gate structures. Traditional Dit extraction methodologies are complicated and require sophisticated instrumentation, complex analysis, and/or prior information related to the device design and fabrication, which is generally unavailable to the consumers of commercial devices. This methodology merely utilizes the transfer characteristics of the device and is straightforward to implement. The Dit analysis using the T3VS method shows that trench devices have significantly lower Dit in comparison to the planar devices, making them more reliable and efficient in practical applications. Furthermore, this study examines the impact of a novel room temperature gate oxide screening methodology called screening with adjustment pulse (SWAP) on the Dit distribution in commercial planar MOSFETs, utilizing the proposed T3VS method. The result demonstrates that the SWAP technique is aggressive in nature and can introduce new defect states close to the conduction band edge. Hence, additional care is needed during screening optimization to ensure the reliability and usability of the screened devices in the consequent applications.