A Fast and Resource-Friendly Hardware Accelerator for Non-Maximal Suppression

The non-maximal suppression (NMS) operator is widely utilized in the post-processing phase of target recognition neural networks. However, its high computation overhead and complex operational process, pose significant challenges to the efficiency of target recognition systems. Some works have been proposed to speed up NMS with FPGA but still cost too much latency and hardware resources. In view of this, we introduce a fast and resource friendly hardware NMS accelerator. Specifically, we first determine the most confidential category of each bounding box with a preprocessing unit, and then determine whether a box should be kept or not quickly by comparing its confidence and calculating the Intersection-Over-Union (IOU) with those of the previously stored boxes in parallel. Experimental results on the Xilinx VCK190 hardware platform reveal that, in comparison to the cutting-edge O3NMS accelerators, the proposed accelerator offers a substantial speedup of approximately 20% while utilizing 21.4% more LUTs and 81.5% less Flip Flops.