Real-Time FPGA Implementation of FFT Architecture Utilizing a Single Butterfly Calculator: Application on Rotor Bars Fault Detection in Induction Motor

This paper presents a new architecture for implementing the Fast Fourier Transforms (FFT) on a field-programmable gate array (FPGA). The proposed architecture comprises one computational butterfly unit comprising one rotation operator and two complex adders. We have provided a detailed explanation of the structure. Our design demonstrates remarkable flexibility when handling increased FFT points. It maintains a fixed utilization of digital signal processing (DSP) resources while experiencing only minor increments in Look-Up Tables (LUTs) and flip-flops. This empowers us to confidently handle a more significant number of FFT points without resource concerns. The FFT architecture is also implemented in real-time on an FPGA, and its application is demonstrated in the context of broken rotor bar detection in induction motors, with the results displayed on a graphical user interface (GUI). The GUI further enhances usability by facilitating signal visualization. The results showcase the efficiency and effectiveness of the implemented architecture for real-time FFT computation in the specified application.