Capacitance Distribution in Charge Pumps With Capacitive Load to Reduce Area and Input Energy

This work introduces a novel design strategy for reducing and optimizing the silicon area and input energy of Dickson charge pumps with a purely capacitive load. The strategy relies on the sizing of the pumping capacitors using a linear distribution, as counter-imposed to the conventional uniform distribution, which allows up to 75% (90% theoretical) of area savings without altering the transient performance. Theoretical analysis shows that the design strategy leads to the additional advantage of decreasing the input energy, thus relaxing the constraints of the ancillary circuitry. Design guidelines are provided to maximize the achievable improvements. Simulation results using a 65-nm CMOS technology confirm the validity of the proposed approach under various practical scenarios.

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Publication Details

Journal
IEEE Transactions on Power Electronics
Published
2025-03-24
DOI
https://doi.org/10.1109/tpel.2025.3554143
Citations
1
Primary Topic
Advanced Battery Technologies Research
Type
article
Field-Weighted Citation Impact
0.68
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article

Capacitance Distribution in Charge Pumps With Capacitive Load to Reduce Area and Input Energy

G. Palumbo, Andrea Ballo, Alfio Dario Grasso
1 citations
IEEE Transactions on Power Electronics
Advanced Battery Technologies Research
0.68
article

Capacitance Distribution in Charge Pumps With Capacitive Load to Reduce Area and Input Energy

G. Palumbo, Andrea Ballo, Alfio Dario Grasso
article en
1 citations

Abstract

This work introduces a novel design strategy for reducing and optimizing the silicon area and input energy of Dickson charge pumps with a purely capacitive load. The strategy relies on the sizing of the pumping capacitors using a linear distribution, as counter-imposed to the conventional uniform distribution, which allows up to 75% (90% theoretical) of area savings without altering the transient performance. Theoretical analysis shows that the design strategy leads to the additional advantage of decreasing the input energy, thus relaxing the constraints of the ancillary circuitry. Design guidelines are provided to maximize the achievable improvements. Simulation results using a 65-nm CMOS technology confirm the validity of the proposed approach under various practical scenarios.

IEEE Transactions on Power ElectronicsVol. 40(9)
University of Catania (IT)
Affordable and clean energy
Openalex Percentile: Top 33%
Advanced Battery Technologies Research
0.68
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