A Multistage CMOS Hall Sensor With 32-ppm/°C Sensitivity Drift for Current Measurement

This article presents a CMOS Hall sensor system for current measurement, featuring a multistage architecture with stepwise amplification and filtering, and an improved temperature compensation strategy by 16-segment piecewise linear interpolation calibration. For the proposed architecture, theoretical analysis is first conducted to explore the effects of the introduction of even-order harmonic distortion and reduced effective gain due to limited analog front-end (AFE) bandwidth and odd-order harmonic distortion caused by modulated offset ripples on the total harmonic distortion (THD) in two-phase spinning current modulation technique (SCMT). It validates that the proposed architecture over traditional approaches can improve THD by at least 20 dB and determines performance benchmarks by modeling and simulation. Furthermore, an improved 16-segment piecewise linear interpolation temperature compensation method is introduced to mitigate temperature drift and integrated into the architecture. Finally, a Hall sensor fabricated using a standard 180-nm CMOS process with an active chip area of 3.42 mm2, achieves a low residual offset of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$45~\mu $ </tex-math></inline-formula>T, a wide bandwidth of 600 kHz, and a minimum sensitivity drift of 32 ppm/°C at a spinning current frequency of 2 MHz.