A Dynamic Voltage-, Frequency-, and Resolution-Scalable (DVFRS) 8–10 b 12.5-to-734 MS/s Non-Interleaved SAR ADC With 0.8-to-5.9 fJ/conv-Step in 22-nm FDSOI

High-efficiency analog-to-digital converters (ADCs) are designed to operate over narrow supply, resolution, and frequency ranges. This work focuses on a scalable ADC architecture and design that can accommodate a wide range of wireless and wireline standards through variable sampling rate, precision, and supply voltage while maintaining high efficiency. The proposed ADC uses a fully dynamic flexible successive-approximation register (SAR) architecture with a wide range of supply adaptation to acclimate across a wide range of sampling rates. Furthermore, it also incorporates resolution-scalable DAC, comparator, and SAR logic to attain efficient conversion at multiple resolutions. A prototype is fabricated in 22-nm fully depleted silicon-on-insulator (FDSOI) technology, with the dynamic voltage-, frequency-, and resolution-scalable (DVFRS) ADC core occupying an active area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$40\times 70~{\mu }$ </tex-math></inline-formula> m. All the measured chips operate at sampling rates from 12.5 to 734 MS/s at 8–10-bit nominal resolution, achieving 46–57.7-dB signal-to-noise-and-distortion ratio (SNDR) and 56–74-dB spurious-free dynamic range (SFDR). A state-of-the-art record Walden and Schreier figure of merit FoMs of 0.84–5.87 fJ/conv-step and 175.4–163.7 dB, respectively, are attained across the operating sampling rates and resolutions.