Origin of performance degradation in vertical gate-all-around transistors using vertical InGaAs nanowires on SOI(111) substrates

Abstract Selective-area growth of InGaAs nanowires (NWs) and vertical gate-all-around (VGAA) transistors using the vertical InGaAs NWs on Silicon-on-insulator (SOI) substrates were characterized toward future three-dimensional integrated circuit applications using III-V NW-based VGAA transistors. On an n-type SOI, the VGAA transistor acts as a field-effect transistor (FET), involving carrier transport and the electrostatic modulation inside the InGaAs NW channels. While on a p-type SOI, the transistor exhibited tunnel FET properties, involving tunnel transport at the InGaAs NW/SOI interface. Characterization of the VGAA transistors with the variation of NW diameter revealed that device properties, including off-leakage current and subthreshold slope, were degraded with large NW diameter due to misfit dislocation at the NW/Si interface.