High-Performance Two-Tier FinFETs With Low-Temperature (≤ 500 °C) Silicide Dopant Segregation Schottky S-D for M3D Circuits

In this work, 2-tier Monolithic 3-Dimentional (M3D) integrated FinFETs and circuits are fabricated based on a low-temperature (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\le 500~^{\circ }$ </tex-math></inline-formula>C) silicide dopant segregation Schottky Source/Drian (SDSS S-D) technology. By forming NiPt silicide followed by B/P implantation and optimizing annealing on top-tier fins, a sharpened Schottky Barrier of the silicide and a high dopant segregation concentration of the impurities are obtained in the improved silicide S-D with maximum process temperature below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$500~^{\circ }$ </tex-math></inline-formula>C. As a result, Low-T 2-tier M3D FinFETs are obtained with I<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\text {ON}}= 646.4~\mu $ </tex-math></inline-formula>A/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m for PMOS and I<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\text {ON}} = 450.6~\mu $ </tex-math></inline-formula>A/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m for NMOS at L<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\text {G}}=500$ </tex-math></inline-formula> nm and a record I<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\text {ON}}=1.84$ </tex-math></inline-formula> mA/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m is achieved for PMOS at L<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\text {G}} =25$ </tex-math></inline-formula> nm under normalized footprint. Furthermore, M3D inverter, ring oscillators, as well as 6T SRAM with this technique are demonstrated, which is promising to provide an effective and low-cost method to achieve low-temperature high- performance silicon circuits in M3D applications.