Dual-Gate Metal-Oxide-Semiconductor Transistors: Nanoscale Channel Length Scaling and Performance Optimization

Dual-gate metal-oxide-semiconductor transistors have attracted considerable interest due to their high threshold voltage control capability, higher drain current, and the ability to alleviate the impact of carrier surface scattering at the channel/dielectric interface. However, their applications in the monolithic integration of scaled devices encounter challenges stemming from the interaction between the pre-treated channel layer and its covering dielectric. Here, we demonstrate the successful realization of a scaled back-end-of-line (BEOL) compatible dual-gate indium–gallium–zinc oxide (IGZO) transistor with a channel length (Lch) scaled down to 150 nm and a channel thickness (Tch) of 4.2 nm. After precisely adjusting the metal ratio to In0.24Ga0.58Zn0.18O and employing O3 as an oxygen precursor for the deposition of Al2O3 as the top-gate dielectric layer, a high maximum current of 1.384 mA was attained under top-gate control, while a high current of 1.956 mA was achieved under bottom-gate control. Additionally, a high current on/off ratio (Ion/off > 109) was achieved for the dual gate. Careful calculations reveal that the field-effective mobility (μeff) reaches 11.68 cm2V−1s−1 under top-gate control and 22.46 cm2V−1s−1 under bottom-gate control. We demonstrate excellent dual-gate low-voltage modulation performance, with a high current switch ratio of 3 × 105 at Lch = 300 nm and 2 × 104 at Lch = 150 nm achieved by only 1 V modulation voltage, accompanied by a normalized current variation higher than 106. Overall, our devices show the remarkable electrical performance characteristics, highlighting their potential applications in high-performance electronic circuits.