A Systematic Evaluation of Novel and Existing Cache Side Channels

CPU caches are among the most widely studied side-channel targets, with Prime+Probe and Flush+Reload being the most prominent techniques.These generic cache attack techniques can leak cryptographic keys, user input, and are a building block of many microarchitectural attacks.In this paper, we present the first systematic evaluation using 9 characteristics of the 4 most relevant cache attacks, Flush+ Reload, Flush+Flush, Evict+Reload, and Prime+Probe, as well as three new attacks that we introduce: Demote+Reload, Demote+ Demote, and DemoteContention.We evaluate hit-miss margins, temporal precision, spatial precision, topological scope, attack time, blind spot length, channel capacity, noise resilience, and detectability on recent Intel microarchitectures.Demote+Reload and Demote+Demote perform similar to previous attacks and slightly better in some cases, e.g., Demote+Reload has a 60.7 % smaller blind spot than Flush+Reload.With 15.48 Mbit/s, De-mote+Reload has a 64.3 % higher channel capacity than Flush+ Reload.We also compare all attacks in an AES T-table attack and compare Demote+Reload and Flush+Reload in an inter-keystroke timing attack.Beyond the scope of the prior attack techniques, we demonstrate a KASLR break with Demote+Demote and the amplification of power side-channel leakage with Demote+ Reload.Finally, Sapphire Rapids and Emerald Rapids CPUs use a non-inclusive L3 cache, effectively limiting eviction-based crosscore attacks, e.g., Prime+Probe and Evict+Reload, to rare cases where the victim's activity reaches the L3 cache.Hence, we show that in a cross-core attack, DemoteContention can be used as a reliable alternative to Prime+Probe and Evict+Reload that does not require reverse-engineering of addressing functions and cache replacement policy.

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Publication Details

Published
2025-01-01
DOI
https://doi.org/10.14722/ndss.2025.230253
Citations
3
Primary Topic
Low-power high-performance VLSI design
Type
article
Field-Weighted Citation Impact
2.19

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article

A Systematic Evaluation of Novel and Existing Cache Side Channels

Fabian Rauscher, Andreas Kogler, Daniel Gruss, Carina Fiedler
3 citations
Low-power high-performance VLSI design
2.19
article

A Systematic Evaluation of Novel and Existing Cache Side Channels

Fabian Rauscher, Andreas Kogler, Daniel Gruss, Carina Fiedler
article en
3 citations

Abstract

CPU caches are among the most widely studied side-channel targets, with Prime+Probe and Flush+Reload being the most prominent techniques.These generic cache attack techniques can leak cryptographic keys, user input, and are a building block of many microarchitectural attacks.In this paper, we present the first systematic evaluation using 9 characteristics of the 4 most relevant cache attacks, Flush+ Reload, Flush+Flush, Evict+Reload, and Prime+Probe, as well as three new attacks that we introduce: Demote+Reload, Demote+ Demote, and DemoteContention.We evaluate hit-miss margins, temporal precision, spatial precision, topological scope, attack time, blind spot length, channel capacity, noise resilience, and detectability on recent Intel microarchitectures.Demote+Reload and Demote+Demote perform similar to previous attacks and slightly better in some cases, e.g., Demote+Reload has a 60.7 % smaller blind spot than Flush+Reload.With 15.48 Mbit/s, De-mote+Reload has a 64.3 % higher channel capacity than Flush+ Reload.We also compare all attacks in an AES T-table attack and compare Demote+Reload and Flush+Reload in an inter-keystroke timing attack.Beyond the scope of the prior attack techniques, we demonstrate a KASLR break with Demote+Demote and the amplification of power side-channel leakage with Demote+ Reload.Finally, Sapphire Rapids and Emerald Rapids CPUs use a non-inclusive L3 cache, effectively limiting eviction-based crosscore attacks, e.g., Prime+Probe and Evict+Reload, to rare cases where the victim's activity reaches the L3 cache.Hence, we show that in a cross-core attack, DemoteContention can be used as a reliable alternative to Prime+Probe and Evict+Reload that does not require reverse-engineering of addressing functions and cache replacement policy.

Graz University of Technology (AT)
Austrian Science Fund
Openalex Percentile: Top 13%
Low-power high-performance VLSI design
2.19
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A Systematic Evaluation of Novel and Existing Cache Side Channels — Fabian Rauscher, Andreas Kogler, et al. · (2025) | TGRS Research Map | TGRS