Recessed p-GaN Gate MIS-HEMT with AlN Interlayer and Buried p-GaN Layer

Herein, the design of a normally off p-GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) comprising a recessed p-GaN gate and a buried p-GaN back barrier layer is reported. The proposed structure is capable to minimize the trade-off between current output and threshold voltage, which is one of the bottlenecks in the design of efficient enhancement mode high electron mobility transistors (HEMTs). The incorporation of both buried p-GaN layer and recessed p-GaN gate structure simultaneously into the conventional device ensures higher threshold voltage along with better current drive capability. In addition, the use of AlN interlayer enhances the 2DEG density in the proposed structure. The device offers a maximum transconductance of about 191 mS/mm compared to the conventional p-GaN gate enhancement mode HEMT which has a value of 172 mS/mm only. The threshold voltages of the p-GaN gate HEMT and the proposed structure are +0.582 and +1.48 V, respectively.

Authors

Institutions

Publication Details

Journal
Semiconductors
Published
2025-03-01
DOI
https://doi.org/10.1134/s1063782624601584
Citations
9
Primary Topic
GaN-based semiconductor devices and materials
Type
article
Field-Weighted Citation Impact
11.32
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Recessed p-GaN Gate MIS-HEMT with AlN Interlayer and Buried p-GaN Layer

P. S. Sreelekshmi, Jobymol Jacob
9 citations
Semiconductors
GaN-based semiconductor devices and materials
11.32
article

Recessed p-GaN Gate MIS-HEMT with AlN Interlayer and Buried p-GaN Layer

P. S. Sreelekshmi, Jobymol Jacob
article en
9 citations

Abstract

Herein, the design of a normally off p-GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) comprising a recessed p-GaN gate and a buried p-GaN back barrier layer is reported. The proposed structure is capable to minimize the trade-off between current output and threshold voltage, which is one of the bottlenecks in the design of efficient enhancement mode high electron mobility transistors (HEMTs). The incorporation of both buried p-GaN layer and recessed p-GaN gate structure simultaneously into the conventional device ensures higher threshold voltage along with better current drive capability. In addition, the use of AlN interlayer enhances the 2DEG density in the proposed structure. The device offers a maximum transconductance of about 191 mS/mm compared to the conventional p-GaN gate enhancement mode HEMT which has a value of 172 mS/mm only. The threshold voltages of the p-GaN gate HEMT and the proposed structure are +0.582 and +1.48 V, respectively.

SemiconductorsVol. 59(3)
APJ Abdul Kalam Technological University (IN)
Sustainable cities and communities
Openalex Percentile: Top 1%
GaN-based semiconductor devices and materials
11.32
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.