A survey on benchmarking and performance evaluation of SOGI based three-phase advanced PLLs with DC offset rejection capability

• The control mechanism of the grid interfacing converter makes sure that the voltage and currents injected by RESs are in-phase with the grid in order to facilitate optimal energy transfer between RESs and the grid. PLLs are frequently used to estimate synchronous data, including grid voltage amplitude and phase angle. Phase-locked deviation, however, might result from inaccurately extracting the fundamental voltage component due to the existence of grid harmonics and Direct Current (DC) offset present in the grid voltage. • The inefficiency of widely used SRF PLL during a non-ideal grid condition and the DSOGI PLL during DC offset affected grid condition necessitated the need for higher order advanced PLLs for robust and precise grid synchronization. • The higher order PLLs like DTOGI PLL and DMSTOGI PLL had a compromise of performance in either case of harmonics or the DC offsets. Additionally, the increased order of the filters of the PLL rather led to increased complexity and slower system dynamics in comparison to the DSOGI PLL. Hence, the advanced SOGI filter based PLLs were found to be an ideal solution for rejection of both the harmonics and DC offsets for accurate estimation of grid data to achieve robust synchronization. • The DTOGI PLL exhibits only a little better filtering effect yet no DC offset rejection than the DSOGI PLL. Whereas, the DMSTOGI PLL exhibits poor filtering effect but with DC offset rejection capacity than the DSOGI PLL. But in order to achieve a robust grid with RESs synchronization with accurate estimation yet with system simplicity, faster dynamics and reduced complexity during implementation, the advanced SOGI based PLLs with DC rejection ability was found to be the best and most suitable. • The purpose of this work is to present a thorough review and examination of several advanced SOGI based PLLs for solving the DC offset issue. These methods involve blocking the DC offset before the PLL input using the advanced Second Order Generalized Integrator (SOGI) based filters for accurate phase extraction. These approaches' design features are discussed, along with the detailed Bode plot analysis of the filters and performance analysis in MATLAB/Simulink evaluating their ability in accurate phase extraction with DC rejection for robust synchronization. The Renewable Energy Sources (RESs) are integrated into the grid through power electronic converters in order to meet the increasing demand for electricity. To enable the best possible energy transfer between RESs and the grid, the grid interfacing converter's control mechanism ensures that the voltage and currents injected by RESs are in phase with the grid. Phase Locked Loops (PLLs), are widely employed in the estimation of synchronous data, such as phase angle and grid voltage amplitude. However, because of the presence of grid harmonics and Direct Current (DC) offset in the grid voltage that cause fundamental frequency oscillations, phase-locked deviation may arise from incorrectly extracting the fundamental voltage component. Other advanced PLLs are sought after due to the inefficiency of the frequently utilized Dual Second Order Generalized Integrator PLL (DSOGI PLL) and Synchronous Reference Frame PLL (SRF PLL) during the DC offsets for grid synchronization. The grid tied RESs synchronization in the DC offset case is still unachievable despite the Second Order Generalized Integrator (SOGI) filter based DSOGI PLL's excellent harmonic rejection capacity. This article provides an in-depth analysis of some advanced SOGI filter based PLL approaches to mitigate the DC offset problem in PLL algorithms. These techniques entail utilizing the advanced structures of the SOGI based filter to block the DC offset prior to the PLL input. These approaches' design features, stability analysis using Bode plots and a comprehensive performance study using MATLAB/Simulink is conducted highlighting their pros and cons to provide an accurate benchmark for the SOGI based PLLs.