Evaluation of 1T-DRAM Based on Novel Triple-Gate Nanosheet RFET With Surrounded SiGe Channel

In this study, a capacitorless 1T-DRAM based on a novel triple-gate nanosheet reconfigurable field effect transistor (RFET) with surrounded SiGe channel (SC-RFET) is first proposed. Due to the additional SiGe storage area under the control gate (CG) and applying positive or negative bias voltages to regulate the injection or extraction of holes from the SiGe storage area, the proposed SC-RFET exhibits significant performance enhancement, particularly in terms of improving sense margin and retention time (RT). Compared to the case based on the traditional triple-gate RFET (TG-RFET) at the room temperature of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$27~^{\circ }$ </tex-math></inline-formula>C, the sense margin of 1T-DRAM based on SC-RFET shows nearly an order of magnitude improvement (from 32.29 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$316.7~\mu $ </tex-math></inline-formula>A/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m), the current ratio increases about three orders of magnitude (from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.465\times 10^{{5}}$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.078\times 10^{{8}}\text {)}$ </tex-math></inline-formula>, and the RT also increases from 1.35 to 99.5 s. Notably, even at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$150~^{\circ }$ </tex-math></inline-formula>C, the RT of our novel 1T-DRAM remains stable at 1.245 s, showcasing the robustness of the proposed RFET. Furthermore, the proposed 1T-DRAM also demonstrates a rapid read time of 2 ns and a write time of 1 ns. Detailed analysis is performed from device physics and operation, and guidelines design of 1T-DRAM cell are presented.