Nonvolatile Capacitive Synapse Utilizing Polar Topological States for Computing-in-Memory

In this work, the ferroelectric capacitor utilizing polar topological states is proposed for the capacitive synapse device in compute-in-memory (CIM). Three-dimensional phase-field simulations coupled with the Poisson and Navier-Cauchy equations are conducted for SrTiO3/PbTiO3/SrTiO3 capacitor as the host system of polar topological states. Using the state-of-the-art in-house tool developed for the purpose, we theoretically demonstrate that the multiple topological states can be programmed with low write voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\leq 1$ </tex-math></inline-formula> V). The pulse schemes are proposed to write the multiple states. We show that more than 2-bit nondestructive read-out (NDRO) with the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on/off</small> ratio of at least 3.7 can be achieved. These results provide strong evidence that the ferroelectric capacitor utilizing the polar topological states is a promising candidate for capacitive synapse devices.