Performance Optimised Architectures of Lightweight HIGHT Cipher for Low-Resource IoT Applications

A major concern in many data-sensitive applications of Internet of Things (IoT) platforms is the security and privacy. The execution-speed, ability to adapt, and processing capacity of IoT systems are limited. Various encryption techniques have been proposed recently to ensure the security of IoTs communication. In this paper, different architectures of HIGHT lightweight block cipher are implemented on the different family of field programmable gate arrays (FPGAs), in which round-based has a smaller number of flip-flops, high-speed architecture has good throughput. In addition, serial RAM-based design has low power consumption and low area consumption of 0.572 W and 34, respectively. Moreover, combined encryption/decryption architecture consumes resources of flip-flop 197, slices of 151, LUTs of 502, and frequency of 249 MHz. The percentage improvement in the area over the previous work is around 135% and 97% in maximum operating frequency, respectively. The results of hardware design are thoroughly evaluated and compared to the most relevant lightweight block ciphers.