Fast parallel implementation of AES based on CUDA and fixed slicing technology

With the advent of the era of big data and 5G communications' massive data, high-speed cryptographic algorithms are in demand. This paper proposes a new fast implementation of the Advanced Encryption Standard (AES) algorithm based on graphics processing unit (GPU) and fixed slicing technology. Based on the structural features of AES, the algorithm's performance can be improved by fixing certain slices of AES and adjusting its linear layer on compute unified device architecture (CUDA). By further adopting full-bit fixed and half-bit fixed implementations of AES, it was found that the time and data throughput of the two methods were similar, but the half-bit fixed implementation used fewer operands. The research results show that the application of fixed slice technology can improve the performance of the AES algorithm and enhance its spatial utilization. Applying the fixed slice technology to implement the AES algorithm can achieve a 2.60-fold and 5.88-fold performance improvement on CPU and GPU, respectively, with the peak acceleration ratio on GPU reaching 310. Compared with existing AES parallel algorithms, the implementation results of this paper have the highest performance improvement of 21.6 times. In summary, GPU and slicing technology can significantly enhance the performance of symmetric cryptography.