Design and Study of Source Pocket Extended Gate Vertical TFET
In this article, we proposed a heterojunction vertical TFET (VTFET) with Silicon germanium (SiGe) source pocket engineering. The proposed device is capable to improve the performances of devices in terms of higher ON current, high ION/IOFF ratio, Reduced leakage current, and lower subthreshold swing (SS). The proposed Vertical TFET structure has been simulated using the commercial Silvaco TCAD tool. A compound semiconductor material SiGe is used in the source region and silicon is used as drain and channel material to enhance the carrier tunneling between source and channel. Transconductance, electric field, energy band diagram, and transfer characteristics are also analyzed in this article.
Authors
- Binay Binod Kumar
- Gaurav Kumar (ORCID: https://orcid.org/0000-0003-2246-6111)
- Nisha Rani (ORCID: https://orcid.org/0009-0006-9455-1138)
- Kavindra Kumar Kavi (ORCID: https://orcid.org/0000-0002-1306-8309)
- Ram Ishwar Vais
- Kamalesh Kumar Sharma (ORCID: https://orcid.org/0000-0001-7924-7468)
- Mahesh Kumar (ORCID: https://orcid.org/0000-0002-5357-7300)
- Abhinav Gupta
- Lavi Tyagi (ORCID: https://orcid.org/0000-0002-2816-7019)
Institutions
- National Institute of Technology Patna (IN)
- Indraprastha Institute of Information Technology Delhi (IN)
- Guntur Medical College (IN)
- Govind Ballabh Pant University of Agriculture and Technology (IN)
Publication Details
- Published
- 2024-11-23
- DOI
- https://doi.org/10.1109/icicat62666.2024.10923491
- Citations
- 3
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.63