Analysis of Low Power Approximate 128x128 bit Vedic Multiplier for Existing Real World FPGAs

In today's environment, research into the implementation of Machine Learning Algorithms in the VLSI sector has increased dramatically. One of the most important requirements for these designs was the employment of multipliers. In order to build a low-power approximate multiplier, in this paper we have built an accurate 128x128 bit Vedic multiplier that uses the Urdhva-Tiryagbhyam sutra, which is one of the sixteen sutras available. This design is built with the logic gates and ripple carry adder designs. For the approximation of the Vedic multiplier, a total of eleven approximate adder designs are compared and analyzed, in which three approximate adders are designed using a 2:1 MUX and the remaining with only the logic gates. This is done in order to generate the comparison of the approximate designs with respect to a multiplexer and without a multiplexer, which is one of the main factors available in the different FPGAs available in the real world. The result with a multiplexer is optimized with the LUTs used by a percentage of 36.56% and the total power by a percentage of 82.46%. And the result without a multiplexer is optimized with the LUTs used by a percentage of 98.93% and the total power by a percentage of 93.95%. The designs are coded using Verilog HDL and synthesized using Xilinx Vivado, which gives accurate area and power values with respect to the FPGAs.