TSPC Latch-Mux Based DET Flip-Flop for Area-efficient and Low-power Applications

Low-powered flip-flop designs are essential in latest electronic devices to fulfill the increased need for energy efficient gadgets, especially in mobile and battery-operated applications. This paper presents an innovative design for a Dual-edge-triggered (DET) flip-flop operating on a True Single-Phase Clock (TSPC). The suggested concept employs Gate Diffusion Input (GDI) technique to design the multiplexer with less dynamic power consumption and area than the current TSPC DET. Cadence Virtuoso Design suite with 45nm CMOS technology is used to simulate the design. The proposed design outperforms the current dual-edge-triggered flip-flop in terms of a reduction in power (8%), area (38%), and power-delay-product, or PDP (18.17%). So, analysis shows that this novel dual-edge-triggered flip-flop is the best choice for low-power and area-efficient applications.