Designing A 8-Bit Pipeline ADC Using Cadence Virtuoso

The demand for high-performance analog-to-digital converter (ADC) integrated circuits (IC) with optimal resolution, sampling rate, and power consumption is increasing due to emerging applications in wireless communications, broad band transceivers, digital-intermediate frequency (IF) receivers, and numerous digital devices. This research work aims to provide a pipeline ADC design technique with low power consumption, while maintaining high speed and resolution. The aim of our paper is to produce pipeline architecture ADC which has high resolution, fast speed, and low power consumption. In the proposed work the Cadence Virtuoso software tool is used. 180nm, 90nm technology is used to create an 8-bit ADC with 1-bit resolution to each stage. Verilog and pipeline architecture require a 1V supply voltage to function.