Design and Performance Analysis of Nanowire FET for Low Power VLSI Applications

In order to meet the growing need for exceptional performance, cost-effective, and compact electronic devices, new transistor topologies like nanowire field-effect transistors (NWFETs) are being investigated for use in VLSI technologies. The thorough conceptual and operational analysis of NWFETs is presented in this study, with an emphasis on how they may be used in future VLSI circuits to operate at high speeds and low power. In comparison to traditional MOSFETs, we show considerable reductions in leakage current and increased subthreshold slope by utilizing the unique electrostatic control of the gate-all-around (GAA) structure intrinsic to NWFETs. This results in decreased power dissipation. Using a range of channel lengths, oxide thicknesses, and supply voltages, our simulations assess the NWFET and optimize its characteristics to minimize power consumption while preserving strong switching efficiency.