Design of an Efficient Encryption and Decryption Modular Exponentiation for Single Word Size

Modular exponentiation (ME) is a mathematical operation that is used for several public-key cryptosystems (PKCs) and other applications. It is a complex task that is an essential computational tool that enables efficient handling of large numbers, especially in cryptography and computer algorithms. Its efficiency is obtained from advanced mathematical techniques like exponentiation by squaring, which is known to reduce computational complexity significantly. In this method, an efficient ME operation i.e. the modular exponentiation method is presented which improves raising any integer x to a power, namely k, and reducing the result to the modulo some integer n. This ME operation is easy to implement on paper but is expensive for resource-constrained devices in terms of the time of computation, energy consumption, etc. To tackle this problem, several different methods of computation have been proposed its implementation efficiently. In this paper, we present the implementation of an efficient ME method for single word size and then implement the method in hardware using Verilog HDL. Then, after implementation, we compare the results of the implementation of our results with two of the most frequently used conventional methods of ME i.e. Montgomery method and the Barret method. The performance parameters like clock cycles, power, and utilization are compared and presented. The low power and faster exponentiation can have potential application in emerging internet of things (IoT) and low power sensor nodes in future.