A 20-bit SAR-Assisted Extended Counting Incremental ADC With a Clock-Controlled PGA Buffer

To optimize small signal acquisition and conversion, analog-to-digital converter (ADC) often requires a programmable gain amplifier (PGA) and buffer. However, there still remains trade-offs among noise, power consumption and drive capability, which present a significant challenge for further improvement. This paper introduces a novel clock-controlled buffer that operates only during the initial 1/4 time of the sampling period, enabling rapid signal establishment while minimizing noise overhead. To achieve high resolution, an incremental ADC (IADC) with extended counting has been employed. The circuit primarily consists of an incremental delta-sigma ADC and the proposed 9-bit successive approximation register (SAR) ADC for extended counting. Fabricated in a standard <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.25~\mu $ </tex-math></inline-formula>m CMOS process, the proposed ADC achieves a 20.58 effective number of bits (ENOB) with extended counting from a 3.3 V supply. The proposed buffer enhanced the overall dynamic performance of the system by facilitating rapid establishment, leading to a 14.75% increase in signal-to-noise ratio (SNR) and a 30% improvement in spurious-free dynamic range (SFDR).