An Ultra-Low-Power Fully-Static Contention-Free Single-Phase-Clock Flip-Flop With Low Area

This paper introduces a Fully-Static, Contention-Free Single-Phase-Clock Flip-Flop for IoT devices. The design objectives are accomplished through three main components. Firstly, the elimination of invalid toggling of internal nodes significantly reduces power consumption. Secondly, a Fully-Static and a Contention-Free structure are achieved by eliminating floating nodes and contention paths, respectively, enhancing robustness. Lastly, area is reduced through logic merging and topology compression. This Flip-Flop is implemented in a 28nm process. Post-simulation results indicate that, at 0.9V, 1GHz and activity rate of 10%/20%, dynamic power of this design is only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.44~\mu $ </tex-math></inline-formula> W/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.88~\mu $ </tex-math></inline-formula> W, resulting in 86.95%/76.44% power reduction compared to traditional MSFF. This design focuses on static power. Static power of this design achieves 0.07nW/0.77nW at 10MHz, 0%, 0.4V/0.9V, 98.91%/97.59% less than MSFF. 10K Monte Carlo simulation confirms that this design maintains 100% functional integrity within the voltage range of 0.4-0.9V. Layout results indicate this design achieves an extremely low area.