High-Speed CMOS Synchronous Binary Counter With Constant Counting Rate

In VLSI design, the counter stands as one of the most fundamental and widely utilized components. It finds extensive applications across various fields, including analog-to-digital converters, time-to-digital converters, frequency dividers, phase-locked loops, frequency synthesizers, and IoT networks. As technology advances, many applications necessitate high-speed counters supporting wider bit-widths. Nevertheless, the conventional synchronous binary counter, renowned for its simplicity, encounters a decline in counting rate as the counter size increases, primarily due to the lengthy signal chain. To overcome this limitation, a pre-scaled structure has been presented, ensuring a consistent counting rate even with increased sizes. In our pursuit of creating a high-speed counter, we incorporate this pre-scaled structure and introduce an early state detection technique to reduce the critical path affecting the counting rate. This enhancement expedites the generation of the enable signal for the subsequent sub-counter. Furthermore, to minimize the delay caused by T-flip-flops in the conventional binary counter, the sub-counters are intelligently designed based on the Johnson counter. In a 28nm CMOS process, the proposed counter achieves an impressive counting rate of 3.7 GHz, and maintains a nearly constant counting rate regardless of counter sizes, showcasing its robust performance.