Linear Tuning of Positive Threshold Voltage in IGZO Thin-Film Transistors via Gate Dielectric Stack Engineering

The positive threshold voltage (VTH) tuning in InGaZnO (IGZO) thin-film transistors (TFTs) has become an urgent issue. In this work, the effect of different ultrathin gate dielectric interlayers (ILs) inserted between the high-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> HfO2 and IGZO is investigated based on the pristine VTH of +0.064 V optimized by IGZO sputtering and post-annealing. By specifically combining varying HfO2 thicknesses and IL types, this initial VTH is linearly modulated to +0.528 V in IGZO devices without noticeable sub-threshold swing (SS) and mobility degradation. Attributed to the dipole and fixed charge modulation at the interface, the devices with 7-nm HfO2 and 2-nm SiO2 IL exhibit optimal results, including the most positive VTH, a decent mobility of 12 cm2/V<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula>s, a well-maintained SS of 84.7 mV/dec, and promoted positive and negative bias stress (PBS/NBS) stability. This VTH modulation technique provides useful guidance for 3D integration such as IGZO 3D-DRAM with high performance.