A ring-oscillator-based 5.2-ps bin-size integrated circuit for time measurements

Abstract High-resolution time measurement is essential in time-of-flight positron-emission tomography and in high-energy physics experiments. The increasing demands for imaging accuracy and detector performance necessitate high-resolution and high-precision timing circuits. Based on a ring-oscillator delay line incorporating a phase-locked loop, a delay-locked loop, and a passive interpolation technique, we have developed a circuit that achieves an average bin size down to 5.2 ps in a 55-nm CMOS process. High resolution poses challenges in bin-size uniformity, multi-channel integration, power consumption, readout bandwidth, and potential bubble codes. In this prototype we primarily focus on achieving high resolution and establishing a test system. Design and simulation results will be presented, with preparations for testing on-going. In the subsequent iterations we will balance other issues and gradually research a production-ready design.