Design and Implementations of LUT based Approximate Adders for FPGAs

This paper presents a novel approach to the design of high-speed, power-efficient adders by leveraging approximation techniques to balance performance with accuracy. Our proposed design addresses the limitations of traditional adders by employing a strategy that truncates the least significant part (LSP) of the adder, resulting in a reduction of approximately 50% in area and power consumption. Additionally, this approach minimizes propagation delay by up to 50% and enhances speed through inner-stage input-output pipelining within the parallel prefix adder framework. The most significant improvement in our design lies in the use of Look-Up Tables (LUTs) for accurate computation while slightly increasing the error margin of approximate adders to optimize parameters. Our comparative analysis reveals that the proposed adder significantly outperforms current LEADx and APEx models in terms of efficiency. Synthesized and simulated using Xilinx Vivado, the new design effectively balances speed, power efficiency, and accuracy.