128-bit Asynchronous Gray Code FIFO using Verilog HDL

This paper presents the design and implementation of a 128-bit Asynchronous Gray Code FIFO using Verilog HDL. The FIFO is designed for bidirectional transfer of data between different clock domains using dual-port RAM memory and gray code for specifying empty and full conditions. To avoid metastability, two 2D flip-flops are used as synchronizers. The design is optimized for speed and efficiency using universal gates and status flags Also, the simulation provides the threshold status flags for write and read operations is 10% and 90%, respectively. The simulation and verification of the design are performed using Xilinx Vivado software and virtually implemented for the Artix 7 Low Voltage FPGA. The design is scalable for larger memory requirements.