Low Power SRAM cell Design Using MTCMOS and Stacking Techniques

Various research has been conducted to create low-power Static Random Access Memory (SRAM) cells due to the increasing demand for power-efficient memory designs. This paper discusses the design and analysis of a low-power SRAM cell that utilizes Multi-Threshold CMOS (MTCMOS) and transistor stacking techaniques simultaneously, which are two commonly used power reduction techniques. By using transistors with different threshold voltages, the MTCMOS technique minimizes leakage power, as does the stacking method, which connects two half size transistors in series instead of a full size transistor to reduce subthreshold leakage. These techniques combine to cosiderably reduce both dynamic and static power consumption in SRAM cells, making them perfect for power-efficient applications like portable devices and IoT systems,mobiles laptops and embedded system designs. The SRAM cell's noise margins and stability are assessed by performing SNR analysis using Cadense Virtuoso and MATLAB under various process circumstances.