Innovations in fibre array coupling and integration for high-bandwidth FPGA multichip packages

The FPGA-based hardware accelerator multi-chip packages (MCPs) presented in this study showcase the first example of 168 edge coupled fibers to one side of an FPGA-based package with a small shoreline of 26.5mm, which will enable co-packaged technology to push towards 50Tbps of aggregated bandwidth on one side of the MCP. The presented study examines the mechanical and optical design constraints of a compact edge coupled MCP, consisting of 3 PICs each with 56 optical channels with narrow spacing between, 3EICs, and an FPGA. Stress relief designs were developed for robust fiber attach to the PIC and the package substrate while minimizing the package size. The die-attachment of the PIC to the substrate introduces a mechanical warpage (bending) of the PIC, which was investigated along with the subsequent effect on optical coupling during fiber array integration. An automated fiber array unit (FAU) attachment process was developed that provided FAU-to-MCP packaging with repeatable results (-2.21±0.43dB insertion loss measured across 48 loopbacks after fiber attachment to 24 packages). This process can also be used for rapid indirect PIC warpage measurements, which allowed additional warpage-induced coupling losses to be estimated for channels without loopbacks, so that specified optical channels could be prioritized during assembly. Methods to mitigate for warpage-induced optical coupling losses were also investigated. The presented automated high channel-count FAU-to-PIC integration procedure and PIC warpage analysis demonstrates a push towards higher-volume manufacturing of co-packaged FPGA multi-chip platforms and higher aggregated bandwidths than previously reported.