SPLIT PUF: Efficient PUF Implementation Using Underutilized FPGA Resource

The Field Programmable Gate Array (FPGA) market has seen significant growth due to the low cost and reduced time to market when compared to ASIC circuits. However, FPGAs’ reconfigurable nature introduces security vulnerabilities that can be exploited by adversaries to obtain sensitive information. Physical Unclonable Functions (PUFs) have shown to be valuable security primitives. By leveraging manufacturing variations in a device, one can generate unique signatures that can be used for authentication and generation of secret keys. However, PUF implementation can be costly, taking up FPGA resources and requiring long design times. In this article, we propose a method which takes advantage of the FPGA look-up table (LUT) architecture to embed the PUF into functional logic circuits, reducing the cost and design time. We provide detailed implementation guidelines and evaluate the PUF’s signature quality and stability under different environmental variations using a set of test-bench circuits. Our results demonstrate the effectiveness of our method in securing FPGA designs while reducing implementation costs and design time.