Quantum Computer Architecture for Quantum Error Correction With Distributing Process to Multiple Temperature Layers

ABSTRACT Quantum computers are capable of performing large‐scale calculations in a shorter time than conventional classical computers. Because quantum computers are realized in microscopic physical systems, unintended change in the quantum state is unavoidable due to interaction between environment, and it would lead to error in computation. Therefore, quantum error correction is needed to detect and correct errors that have occurred. In this paper, we propose quantum computer architecture for quantum error correction by taking account that the components of a quantum computer with quantum dots in silicon are divided into multiple temperature layers inside and outside the dilution refrigerator. Based on the required performance and possible processing capacity, each component was distributed in various temperature layers: the chip with qubits and the chip for generation of precise analog signals to control qubits are placed on 100 mK and 4 K stages inside the dilution refrigerator, respectively, while real‐time digital processing is performed outside the dilution refrigerator. We then experimentally demonstrate the digital control sequence for quantum error correction combined with a simulator which simulates quantum states based on control commands from the digital processing system. The simulator enables the proof‐of‐principle experiment of system architecture independent of the development of the chips. The real time processing including determination of feed‐forward operation and transmission of feed‐forward operation commands is carried out by a field‐programmable gate array (FPGA) outside the dilution refrigerator within 0.01 ms for bit‐flip or phase‐flip error corrections. This is a sufficiently short time compared to the assumed relaxation time, which is the approximate time that the quantum state can be preserved, meaning that our proposed architecture is applicable to quantum error correction.

Authors

Institutions

Publication Details

Journal
Concurrency and Computation Practice and Experience
Published
2025-03-19
DOI
https://doi.org/10.1002/cpe.8351
Primary Topic
Quantum Computing Algorithms and Architecture
Type
article
Field-Weighted Citation Impact
0.00

Funders

Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Quantum Computer Architecture for Quantum Error Correction With Distributing Process to Multiple Temperature Layers

Hiroyuki Mizuno, Chihiro Yoshimura, Ryuji Ukai
Concurrency and Computation Practice and Experience
Quantum Computing Algorithms and Architecture
article

Quantum Computer Architecture for Quantum Error Correction With Distributing Process to Multiple Temperature Layers

Hiroyuki Mizuno, Chihiro Yoshimura, Ryuji Ukai
article en

Abstract

ABSTRACT Quantum computers are capable of performing large‐scale calculations in a shorter time than conventional classical computers. Because quantum computers are realized in microscopic physical systems, unintended change in the quantum state is unavoidable due to interaction between environment, and it would lead to error in computation. Therefore, quantum error correction is needed to detect and correct errors that have occurred. In this paper, we propose quantum computer architecture for quantum error correction by taking account that the components of a quantum computer with quantum dots in silicon are divided into multiple temperature layers inside and outside the dilution refrigerator. Based on the required performance and possible processing capacity, each component was distributed in various temperature layers: the chip with qubits and the chip for generation of precise analog signals to control qubits are placed on 100 mK and 4 K stages inside the dilution refrigerator, respectively, while real‐time digital processing is performed outside the dilution refrigerator. We then experimentally demonstrate the digital control sequence for quantum error correction combined with a simulator which simulates quantum states based on control commands from the digital processing system. The simulator enables the proof‐of‐principle experiment of system architecture independent of the development of the chips. The real time processing including determination of feed‐forward operation and transmission of feed‐forward operation commands is carried out by a field‐programmable gate array (FPGA) outside the dilution refrigerator within 0.01 ms for bit‐flip or phase‐flip error corrections. This is a sufficiently short time compared to the assumed relaxation time, which is the approximate time that the quantum state can be preserved, meaning that our proposed architecture is applicable to quantum error correction.

Concurrency and Computation Practice and ExperienceVol. 37(6-8)
Hitachi (Japan) (JP)
Moonshot Research and Development Program
Openalex Percentile: Top 98%
Quantum Computing Algorithms and Architecture
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.