Development of high-speed serializer transmitters in 180-nm technology for CEPC vertex detector readout electronics

Abstract The TaichuPix chip, designed as a dedicated monolithic active pixel sensor for CEPC vertex detector R&D, requires a raw data rate of up to 3.84 Gbps and a power consumption of less than 25 mA/Gbps for the serializer circuit. The initial prototype TaichuPix1 achieved a maximum data rate of 3.36 Gbps but exhibited significant jitter and current issues. Subsequently, two 4-Gbps serializers were developed and optimized to meet the specified requirements. Despite encountering a bias issue initially, test results demonstrate that the root mean square (RMS) jitter of both phase-locked loop (PLL) clocks is less than 1.8 ps. A revision was implemented to address the bias problem by utilizing simple diode-connected transistors to provide the reference current. Tests conducted revealed a clear eye diagram at 4 Gbps, with a total jitter of 62.1 ps, power consumption of 151.2 mW, and the RMS jitter of the ROPLL less than 1.4 ps.