Scalable in-memory compute optical processor

The traditional von Neumann architecture faces significant challenges, leading to increased latency and energy consumption due to data transfers and bandwidth limitations between processing and memory units. To address this, we propose a novel scalable in-memory optical compute processor chip that integrates processing directly within a high-speed (⪆ 20 GHz) photonic SRAM, eliminating separate units for enhanced efficiency. Our design combines the speed of optical analog computing (2^N/2 -level, N/2-bit input) with the control of a N/2- bit digital memory, delivering high-fidelity N-bit output in every cycle using a single wavelength channel. This system is scalable to multiple wavelength channels using dense wavelength division multiplexing for hyperspectral encoding, enabling massive parallelism. By performing computations within the memory, our scalable optical in-memory compute processor effectively addresses the von Neumann bottleneck, paving the way for high-speed, high-bandwidth, low-power processors for demanding computational tasks. Additionally, we present a hardware-algorithm co-design architecture for the proposed optical compute engine, optimized and evaluated to achieve a sustained performance of 17 PetaOps with 8-bit precision on the Matricized Tensor Times Khatri-Rao Product (MTTKRP), a key computational kernel in tensor decomposition and scientific applications.