A 28-GHz 36.75-fs _rms -Jitter Single-Stage Differential Sampling PLL With Accelerated Slide Locking and Sampling Voltage Shift Technique

This article presents a 28-GHz, sub-40-fs-jitter single-stage differential sampling phase-locked loop (DSPLL) with accelerated slide locking (ASL) and sampling voltage shift technique. To solve the cycle slips caused by the limited linear detection range (DR) of the differential sampling phase detector (DSPD), the detailed frequency capture behavior is analyzed and the ASL technique is introduced to eliminate cycle slips during the frequency pull-in stage. Additionally, a sampling voltage shift DSPD (SVS-DSPD) is employed to adjust the sampling voltage position, which reduces the variation in the sampling voltage for better in-band phase noise (PN). A dual-core voltage-controlled oscillator (VCO) is utilized to achieve a 3-dB out-of-band PN reduction. Fabricated in 65-nm CMOS process, the proposed DSPLL demonstrates a jitter performance of 36.75-fsrms and a locking time of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.66~\mu $ </tex-math></inline-formula>s. Furthermore, the measured power is 32.69 mW at 28-GHz output, resulting in an figure-of-merit jitter (FOMJ) of −253.6 dB and an FOMN of −275 dB.