Evaluation of FONOS FDSOI FET for Synapse-Inspired Artificial Neural Network

In this article, a well calibrated FDSOI ferroelectric (Fe)-FET/FeFET is gate-stacked with a charge trap nitride (CTN) for investigating memory and synaptic applications. The CTN is sandwiched between Fe and silicon channel of FeFET to obtain ferroelectric/oxide/nitride/oxide/semiconductor (FONOS) FET for improved memory and synaptic applications. This approach of using both Fe and CTN layers to improve memory and synaptic applications is labeled as hybrid approach. Since, both the Fe or CTN as a standalone gate-stack dielectric can give threshold-voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{T}$ </tex-math></inline-formula>) shift leading to hysteresis transfer characteristics with a program (PGM)/erase (ERS) schemes that predict a memory window (MW). The FeFET uses spontaneous polarization (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{S}$ </tex-math></inline-formula>) to obtain memory operation which offer low power and area. The CTN uses highly mature and reliable charge-trapping-memory (CTM)-based e<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}^{-} $ </tex-math></inline-formula>/h+ trapping <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Leftrightarrow $ </tex-math></inline-formula> de-trapping mechanism with PGM/ERS scheme to obtain MW that has high-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{T}$ </tex-math></inline-formula> (HVT) and low-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{T}$ </tex-math></inline-formula> (LVT) transfer characteristics. Hence, a combination of these leading to a FONOS FET architecture, which is investigated for improved memory properties like MW and retention followed by examining on synaptic attributes for realistic device training accuracy toward artificial neural networks (ANNs). From the investigations: 1) FONOS memory device has predicted improvement in MW with 2.65 V for 8-nm thick CTN layer and retention of Fe-electric field (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E_{\mathrm { Fe}}$ </tex-math></inline-formula>) and charge density for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx 11$ </tex-math></inline-formula> years and 2) synaptic device has shown an accuracy of 93% for MNIST digit dataset in ANNs. These predictions from the FONOS FET aimed at providing hybrid solutions to next-generation devices with extended applications in memory and neuromorphic applications with reliable device operation.