An Efficient Location-Connection-Decoupling Layout Design Method for Multi-Chip SiC Modules With Low Electrical and Thermal Impedance

Design automation methods have recently garnered significant research interest in providing effective and advanced tools for generating optimal layout solutions for power modules. However, when addressing high-power silicon carbide (SiC) modules with numerous paralleled power dies, design efficiency, and effectiveness have become critical challenges. This article introduces a highly efficient location-connection-decoupling layout design automation method for multichip SiC power modules. The method focuses on the simultaneous minimization and equalization of electrothermal impedance. To minimize the calculation time, precise copper trace connection processes are decoupled, and an efficient copper expansion strategy is proposed for generating the base copper connections. The decoupling facilitates a reduction in the overall time required to achieve an advanced power module layout design. The proposed method is applied to the layout designs of three SiC power modules with varying numbers of power dies. The efficiency and effectiveness of the proposed method are demonstrated through a comparison of the modules’ operational performances and the time required, as determined by the sequencing method. A prototype of the module has been showcased. Various electrical and thermal tests are conducted, and the results validate the feasibility of the proposed design method.