A Time and Energy-Efficient Asynchronous Hybrid-Searching Auto Frequency Calibration for a 3.2 GHz Phase-Locked Loop

Wide-band wireless system-on-chip demands phase-locked loops(PLL) designed with multi-band voltage controlled oscillators (VCO), which requires auto frequency calibration (AFC) for frequency presetting. This paper proposes a high-speed energy-efficient integrated AFC with asynchronous hybrid searching technique. The asynchronous architecture breaks the minimum limit of search time, while the hybrid method overcomes nonmonotonic variation of frequency errors in binary search. A true single-phase clock (TSPC)-based RF digital counter further accelerates AFC by directly quantizing the VCO output frequency. In this paper, a 3.2GHz PLL is presented utilizing the high-speed AFC to achieve fast locking performance. Implemented in 28nm CMOS technology, the proposed AFC for a 7-bit VCO achieves a calibration time of 0.88-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.74\boldsymbol {\mu }$ </tex-math></inline-formula>s across available tuning range, while the time of each step reaches 120ns level. With the aid of AFC, the prototype PLL reaches settle in less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.8\boldsymbol {\mu }$ </tex-math></inline-formula>s, while achieving 318.2fs integrated jitter and -64.3dBc reference spur. The Figure-of-Merit (FoM) of the 3.2GHz PLL achieves -239.66dB for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {FoM}_{\text {jitter}}$ </tex-math></inline-formula>, and -186.16dB for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {FoM}_{\text {T}_{\text {S}}}$ </tex-math></inline-formula>.