LOW-LATENCY APPROXIMATE ADDERIN FPGA

Approximate computing has gained significant attention for applications where absolute precision isnot critical, such as image processing, machine learning, and signal processing. The proposeddesign divides the addition process into two stages: a main sub-adder for high-speed approximatecomputation and an error sub-adder for refining accuracy. By limiting carry propagation in the mainsub-adder, the critical path delay is significantly reduced, achieving low latency. Simultaneously,the error sub-adder operates in parallel to correct errors, ensuring a balance between performanceand precision. Experimental results demonstrate the design’s superior trade-off between speed,accuracy, and energy efficiency compared to conventional adders. The proposed architecture ishighly scalable and suitable for resource-constrained and performance-critical applications, such asreal-time image processing and low-power machine learning accelerators.