A Parallelized Neutron Radiation Testing Technique to Understand Failures Within a Complex SoC

Complex system on chip (SoC) is increasingly used in embedded applications where both high computing performance and low power consumption are required. These devices are especially important in embedded environments where safety and reliability are critical, such as advanced driver assistance systems (ADASs) and space applications. The failure modes and failure rates of these devices due to single-event effects are not well understood, and methods for testing these devices are tedious and time-consuming. This work introduces a methodology for simultaneously testing multiple components of an SoC device. This methodology is used to evaluate the failure modes of several components within an AMD UltraScale+ multiprocessor SoC (MPSoC) device under neutron radiation. The results from two neutron beam tests are described and compared.

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Publication Details

Journal
IEEE Transactions on Nuclear Science
Published
2025-03-17
DOI
https://doi.org/10.1109/tns.2025.3551657
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
Type
article
Field-Weighted Citation Impact
0.00

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article

A Parallelized Neutron Radiation Testing Technique to Understand Failures Within a Complex SoC

Jeffrey Goeders, Michael Wirthlin, Maria Kastriotou, Weston Smith
IEEE Transactions on Nuclear Science
Integrated Circuits and Semiconductor Failure Analysis
article

A Parallelized Neutron Radiation Testing Technique to Understand Failures Within a Complex SoC

Jeffrey Goeders, Michael Wirthlin, Maria Kastriotou, Weston Smith
article en

Abstract

Complex system on chip (SoC) is increasingly used in embedded applications where both high computing performance and low power consumption are required. These devices are especially important in embedded environments where safety and reliability are critical, such as advanced driver assistance systems (ADASs) and space applications. The failure modes and failure rates of these devices due to single-event effects are not well understood, and methods for testing these devices are tedious and time-consuming. This work introduces a methodology for simultaneously testing multiple components of an SoC device. This methodology is used to evaluate the failure modes of several components within an AMD UltraScale+ multiprocessor SoC (MPSoC) device under neutron radiation. The results from two neutron beam tests are described and compared.

IEEE Transactions on Nuclear ScienceVol. 72(4)
Brigham Young University (US), Science and Technology Facilities Council (GB)
Defense Threat Reduction Agency
Climate action
Openalex Percentile: Top 96%
Integrated Circuits and Semiconductor Failure Analysis
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