A Parallelized Neutron Radiation Testing Technique to Understand Failures Within a Complex SoC
Complex system on chip (SoC) is increasingly used in embedded applications where both high computing performance and low power consumption are required. These devices are especially important in embedded environments where safety and reliability are critical, such as advanced driver assistance systems (ADASs) and space applications. The failure modes and failure rates of these devices due to single-event effects are not well understood, and methods for testing these devices are tedious and time-consuming. This work introduces a methodology for simultaneously testing multiple components of an SoC device. This methodology is used to evaluate the failure modes of several components within an AMD UltraScale+ multiprocessor SoC (MPSoC) device under neutron radiation. The results from two neutron beam tests are described and compared.
Authors
- Jeffrey Goeders (ORCID: https://orcid.org/0000-0002-9822-6926)
- Michael Wirthlin (ORCID: https://orcid.org/0000-0003-0328-6713)
- Maria Kastriotou (ORCID: https://orcid.org/0000-0003-1010-2396)
- Weston Smith
Institutions
- Brigham Young University (US)
- Science and Technology Facilities Council (GB)
Publication Details
- Journal
- IEEE Transactions on Nuclear Science
- Published
- 2025-03-17
- DOI
- https://doi.org/10.1109/tns.2025.3551657
- Primary Topic
- Integrated Circuits and Semiconductor Failure Analysis
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Defense Threat Reduction Agency