Test Templates to Guide Test Generation for Single-Cycle Gate-Exhaustive Faults
Advanced fault models, such as the defect-aware, cell-aware, and gate-exhaustive fault models, associate several faults with each standard cell or gate of a design. Test generation procedures, including ones that target advanced fault models, produce incompletely specified tests, or test cubes, to support test compaction and test data compression. The key contribution of this article is to generalize the concept of a test cube into that of a test template for fault models where several faults are associated with the same standard cell or gate. Considering single-cycle gate-exhaustive faults as an example, a test template π i for a gate G i with a set of faults F i captures input values that are common to all the tests for the faults in F i while allowing other input values to be different for different faults in F i . A new value, denoted by v , designates a value that is not common to all the inputs. A test template is useful, since faults in F i share many of the same activation and propagation conditions, and learning the common input values of their tests can reduce the search space for test generation. The effectiveness of using test templates to guide test generation is demonstrated by considering single-cycle gate-exhaustive faults that are not detected by a given test set. Such faults are hard to detect. As part of the test generation procedure developed in this article, merging of test templates is carried out for increasing the fault coverage, and additional tests are generated by specifying the v values of test templates. The implementation of the test generation procedure was performed in an academic simulation environment using academic software tools, and the results are reported for benchmark circuits.
Authors
- Irith Pomeranz (ORCID: https://orcid.org/0000-0002-5491-7282)
Institutions
- Purdue University West Lafayette (US)
Publication Details
- Journal
- ACM Transactions on Design Automation of Electronic Systems
- Published
- 2025-03-17
- DOI
- https://doi.org/10.1145/3724395
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.00