A Coding Efficiency-Aware Hardware Design for VVC Affine Motion Estimation Reconstructor
Editor’s notes: This article proposes a specialized hardware architecture for the VVC affine motion estimation reconstructor. The design aims to maintain high coding efficiency while enabling real-time processing of UHD video. —Ney Calazans, Federal University of Santa Catarina (UFSC), Brazil —Bruno Zatt, Federal University of Pelotas (UFPel), Brazil
Authors
- Guilherme Corrêa (ORCID: https://orcid.org/0000-0002-2739-6194)
- Denis Maass (ORCID: https://orcid.org/0009-0001-5006-426X)
- Murilo Perleberg (ORCID: https://orcid.org/0000-0002-1398-5342)
- Luciano Agostini (ORCID: https://orcid.org/0000-0002-3421-5830)
- Marcello M. Muñoz (ORCID: https://orcid.org/0000-0003-0627-526X)
- Marcelo Porto (ORCID: https://orcid.org/0000-0003-3827-3023)
Institutions
- Universidade Federal de Pelotas (BR)
Publication Details
- Journal
- IEEE Design and Test
- Published
- 2025-03-17
- DOI
- https://doi.org/10.1109/mdat.2025.3551896
- Citations
- 3
- Primary Topic
- Real-time simulation and control systems
- Type
- article
- Field-Weighted Citation Impact
- 3.64
Funders
- Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
- Conselho Nacional de Desenvolvimento Científico e Tecnológico
- Fundação de Amparo à Pesquisa do Estado do Rio Grande do Sul