An Adaptive Body Tuned Sense Amplifier for Energy Efficient In-Memory Computing

This brief presents a body tuned sense amplifier for in-memory computing. The body potential of one of the PMOS transistor is adaptively regulated to implement the logic gates. The designed sense amplifier is implemented with conventional 6T SRAM cell without requiring any additional reference voltage for computing. Further, the proposed adaptive mechanism significantly reduces the energy consumption per bit to 15.25 fJ/bit, which is minimum as compared to the state-of-the-art. The design is implemented in 65 nm technology with a supply voltage of 1 V. The performance of design is validated through Monte Carlo simulations and corner analysis. The designed sense amplifier after post layout simulations results in 100% yield and the worst case delay of 90 ps.